1. Is throughput the same as individual instruction latency?
- No
- Yes
- Only in a pipeline
Check the answer and reasoning
No
Throughput counts completed work per time; latency measures one task’s elapsed time.
CS / A2 level
Advanced architecture and operating systems
Pipelining overlaps instruction stages; parallel processing divides work across processing resources. Hazards, communication and serial sections limit achievable speed-up.
Learning objectives
- Explain advanced architecture and operating systems using a concrete example.
- Apply the worked method and justify each step.
- Recognise the limitation described in the final check.
The big idea
Pipelining overlaps instruction stages; parallel processing divides work across processing resources. Hazards, communication and serial sections limit achievable speed-up.
Virtual memory maps logical addresses to physical storage. Scheduling and resource management balance response, throughput and fairness; a page fault requires loading a missing page rather than proving an invalid program.
Worked example
Four pipeline stages each take one cycle. After filling, what ideal throughput is possible?
Follow the solution
Overlapping stages can finish one instruction each cycle, although each instruction still traverses four stages.
Investigate and explain
Predict the worked result before calculating. Change one input, record the new result, and explain which assumptions still hold.
Use the prediction activity below; a local model appears only where it supports this topic.
Check your understanding
2. Four pipeline stages each take one cycle. After filling, what ideal throughput is possible?
- Four cycles between every completion
- One instruction per cycle
- Zero cycles per instruction
Check the answer and reasoning
One instruction per cycle
Overlapping stages can finish one instruction each cycle, although each instruction still traverses four stages.
3. Does doubling processor count always halve execution time?
- Yes
- Only with enough RAM
- No
Check the answer and reasoning
No
Serial work, coordination and uneven workloads constrain parallel speed-up.